The invention is located chiefly in the field of electrically modifiable non-volatile integrated circuit memories and relates more particularly to FLASH EEPROM type memories.
The methods used to manufacture integrated circuits very often cause defects. Hence, after manufacture, each integrated circuit is subjected to tests designed to detect the presence of such defects. Thus, in the case of non-volatile memories which, after manufacture, normally have all their memories cells erased, it is first of all ascertained that the memory array is blank by making a routine reading of all the addresses so as to ensure that each memory cell is truly erased. Write commands are then sent to specified addresses so as to program the corresponding cells. Then, the memory is re-read for these very same addresses and any divergence between the data elements that should have been written and the data elements read points to the existence of a defect.
For memories with large capacities, it is essential to reduce the testing time needed for the detection of defects and hence to achieve the optimal organization of the complete testing of the product, namely the testing of all the possible configurations of the programmed or erased states of the entire memory space. Since the memories are generally organized in a matrix formed by rows and columns of cells, it is possible to limit the number of configurations to be tested while at the same time having significant information on the integrity of the memory after each step of the test.
Thus, since the address of a cell (or of a set of cells forming a word) is formed by a row address and a column address corresponding respectively to the least significant bits and the most significant bits of the address, it is possible, for example, to verify that the row decoders are working properly by the successive programming of all the cells of the first row. To this end, the programming of the cells whose addresses have their most significant bits at zero is activated. These same addresses are then re-read and it is ascertained that the data elements read truly correspond to programmed cells. Similarly, it is possible to verify the column decoders by successively programming the cells whose addresses have their least significant bits at zero. It is also possible to verify the absence of interaction between the row decoders and column decoders by programming the diagonal of the matrix. Finally, to detect the possible interactions between the cells, all the cells whose addresses have most significant bits and least significant bits with the same parity are programmed so as to set up checkerboards of programmed cells. The procedure is ended by programming the cells in a complementary checkerboard pattern.
These few simple tests are a first step used for the speedy detection of frequently encountered defects.
Up till now, the testing operations such as those just described have been carried out by means of a tester connected to the external terminals of the integrated circuit to be tested. The tester is a unit programmed for the automatic generation of the addresses and data elements corresponding to the test profiles to be carried out and for the applying of the corresponding commands to the terminals of the circuit. The tester then activates the reading of the memory for the same addresses and compares the data elements that are read with the data elements that are written.
This method therefore implies a complete writing operation for each cell (or each word) to be programmed. The result thereof is that the time needed to carry out the complete testing of each memory is relatively lengthy especially if it is a large-capacity memory and if the communications protocol requires several cycles for each write command.
Thus, the invention is aimed at reducing the testing time by replacing the external write commands by automatic internal programming mechanisms.
To this end, an object of the invention is a non-volatile memory that is electrically modifiable by erasing and programming operations, said memory comprising:
at least one matrix of memory cells organized in rows and columns, PA1 supply means to apply erasure and programming voltages to said rows and columns, said programming voltages being applied selectively to the rows and columns identified respectively by row addresses and column addresses, PA1 an address generator comprising counting means activated by an incrementation signal, PA1 means to control said supply means and said address generator, said erasure operation consisting of the performance, by said control means, of a first pre-erasure programming algorithm followed by a second erasure algorithm, said first algorithm consisting in activating the incrementation of said counting means so that it successively gives all the possible values of said row addresses and column addresses and, for each address value given, in activating said supply means so that they give said programming voltages, said memory being one wherein said counting means comprise a row counter and a column counter respectively giving said row address and column address values, and wherein said address generator is designed to work according to a normal mode and at least one test mode, the operation in test mode(s) being conditioned by a first test word, said normal mode consisting in incrementing said row counter exclusively by said incrementation signal and said column counter exclusively by an overflow signal of said row counter, said test mode or modes consisting in permitting the incrementation, by said incrementation signal, of said row counter and/or the incrementation of said column counter as a function of said first test word.
Since the implementation of the test modes uses, to a large extent, means necessary in normal operation (such as the pre-erasure programming algorithm and the counting means), the invention furthermore has the advantage of entailing very little extra cost.
According to the invention, it is possible to provide for a first test mode to program the first row by incrementing solely the row counter or else a second test mode to program the first column by incrementing solely the column counter or else a third test mode to program the diagonal by incrementing the row and column counters simultaneously.
Certain memories have several matrices of memory cells each defining a sector that can be selected by a sector address. These memories are generally designed so that it is possible to achieve the selective erasure of any one of the sectors or all these sectors (total erasure). The counting means can then be broken down into a row counter, a column counter and a sector counter, the sector counter being designed to carry out the total erasure of the memory.
Thus, according to another aspect of the invention, a fourth test mode consists in simultaneously incrementing said row and column counters by said incrementation signal and in activating the incrementation of said sector counter by a signal relating to the overflow of said column counter.
In order to detect the interactions among several sectors, it is advantageously provided that the overflow signal of said column counter will activate the incrementation of said column counter when the address generator works according to said fourth test mode. This arrangement indeed makes it possible to shift the diagonals of programmed cells when going from one sector to the next one.
To enable the performance of other tests producing alternations of programmed and non-programmed cells of each matrix, the invention furthermore provides that the control means will comprise at least one data generator which can be placed in a first state or a second state and which, during the performance of said first algorithm, controls said supply means so that they apply said programming voltages provided that said data generator is in said first state, said data generator being designed to work according to a normal mode or at least one test mode, the operation in test mode being conditioned by a second test word, said operation in normal mode consisting in placing said data generator in said first state, the operation in test mode consisting in placing said data generator in said second state as a function of said second test word and addresses given by said data generator.
The presence of the data generator just defined makes it possible, especially, to obtain checkerboard type test modes. To this end, it is enough to make the address generator work according to its normal mode and place the data generator in its first state as a function of the respective parities of the values contained in the row and column counters. Thus, an even parity or odd parity checkerboard is obtained depending on whether the condition laid down is that the row and column address values should have the same parity or that they should have opposite parities.
An object of the invention is also an integrated circuit incorporating a memory having the characteristics that have just been explained. Advantageously, the integrated circuit will also contain a test circuit to give the test words in response to test commands external to the integrated circuit.